Static linearity testing is vital to the economics of analog-to-digital converter (ADC) manufacturing, which is why researchers in academia and business have put a big quantity of labor into growing extra environment friendly ADC testing strategies.
A earlier article on this collection launched the servo-loop methodology for testing ADC static parameters. On this installment, we’ll focus on the histogram methodology usually and discover the makes use of of a linear ramp histogram take a look at particularly.
First, although, let’s check out the most important shortcomings of the servo-loop methodology that made growing this different testing methodology mandatory.
Servo-Loop Methodology: ADC Noise Impact
Whereas the servo-loop methodology is a well-liked industrial testing approach, it doesn’t present optimum effectivity for ADCs with giant, input-referred noise. Its accuracy over a given measurement time falls considerably wanting the Cramér-Rao sure, which represents the theoretical optimum accuracy. Determine 1 compares the efficiency of a servo-loop take a look at, denoted because the “typical” plot, with the accuracy predicted by the Cramér-Rao sure.
Determine 1. Servo-loop take a look at efficiency accuracy in comparison with the theoretical optimum. Picture used courtesy of P. Capofreddi
As you may see, the servo-loop methodology can’t present optimum effectivity at increased noise ranges.
The servo-loop methodology would possibly work satisfactorily for a 14-bit ADC with low sufficient input-referred noise. Nonetheless, a lot of at the moment’s high-resolution ADCs have a excessive enter bandwidth, resulting in peak-to-peak, input-referred noise in extra of two LSB (least vital bits). For this reason we want testing strategies that may derive the ADC switch perform no matter its noise stage.
Histogram Testing of ADCs
Often known as the code density take a look at, the histogram take a look at is by far the most well-liked methodology for testing ADC static parameters. The accuracy achieved by this methodology over a given measurement time could be very near the theoretical optimum worth specified by the Cramér–Rao sure (Determine 2).
Determine 2. Histogram take a look at efficiency accuracy in comparison with the theoretical optimum. Picture used courtesy of P. Capofreddi
In contrast to the servo-loop methodology, which immediately measures the ADC transition factors, the histogram methodology makes use of a statistical evaluation of the converter output to find out the transition factors. Determine 3 illustrates the essential thought behind histogram testing.
Determine 3. Clockwise from prime proper—the switch attribute of a great 3-bit ADC, the rotated waveform of a full-scale ramp utilized to the ADC enter, and the rotated histogram of that waveform. Picture used courtesy of Steve Arar
Determine 3 could be divided into three plots, indicated above by letter designations. Determine 3(a) reveals the switch attribute of a great 3-bit ADC. Determine 3(b) reveals the rotated waveform of a full-scale ramp utilized to the ADC enter. The ramp is assumed to have a set slope; we all know that the switch perform of a great ADC has uniform steps.
For instance, think about the step akin to codes 011 and 100. These two steps have the identical width, so the ramp sign ought to produce the identical voltage change between the steps’ transition factors ((Delta V_{1}~=~Delta V_{2})). Since (Delta V_{1}~=~Delta V_{2}), and the slope of the ramp is fixed, it follows that (Delta t_{1}~=~Delta t_{2}). Because of this the ramp enter falls throughout the enter vary of various codes for a similar period of time. In different phrases, the ADC spends the identical period of time at every of the output codes.
Primarily based on this statement, we are able to accumulate a lot of output samples and create a histogram of code occurrences. Every “bin” within the histogram represents an output code, and the depend of every bin offers the variety of occasions that code happens. This depend is proportional to the width of the corresponding step within the ADC switch perform.
Determine 3(c) reveals the rotated histogram for this instance—notice that the bins akin to codes 001 by way of 110 all have the identical depend (8, on this instance). For the reason that first and final steps within the best ADC are usually outlined as having a width of 0.5 LSB and 1.5 LSB, the counts for the bins akin to codes 000 and 111 are, respectively, 4 and 12.
One may argue that the primary and final codes don’t even have an outlined width, because the first code doesn’t have a decrease sure and code 111 doesn’t have an higher sure. If the enter overdrives the ADC, these two codes can happen extra usually than anticipated. In reality, in sensible histogram testing, the amplitude of the ramp enter is chosen to barely exceed each ends of the ADC enter vary. That is executed to make sure that the enter sign workouts all codes of the ADC. Because of this, the primary and final bins are usually ignored within the histogram methodology.
Enter Alerts Generally Utilized in Histogram Testing
The take a look at illustrated in Determine 3 is called the linear ramp histogram take a look at. As that identify suggests, it makes use of a ramp enter. Nonetheless, the enter for a histogram take a look at doesn’t need to be a ramp—sinusoidal inputs are a standard selection, and any enter with a identified chance distribution perform (PDF) can be utilized. We solely have to compute the output PDF that a great ADC produces for the kind of enter sign used within the take a look at. Subsequent, evaluating the measured output histogram with the theoretical one, we are able to decide the precise transition factors of the ADC.
Utilizing a Linear Ramp Histogram Check to Discover DNL Error
Now that we’ve mentioned the speculation behind histogram testing, let’s use the histogram methodology to seek out the differential nonlinearity (DNL) error of an instance ADC.
To begin with, think about the non-ideal 3-bit ADC proven in Determine 4 (purple curve).
Determine 4. Superb (blue) and non-ideal/nonlinear (purple) instance ADC response. Picture used courtesy of Steve Arar
The DNL plot of this instance ADC is offered beneath, in Determine 5. Observe that code 5 (101) is lacking.
Determine 5. Differential nonlinearity of the instance ADC. Picture used courtesy of Steve Arar
Now, utilizing the above switch perform with a full-scale vary of 1 V, we’ll digitize the periodic ramp at a sampling charge of 40 kHz. Determine 6 reveals the consequence.
Determine 6. Repeating periodic linear ramp enter for instance ADC histogram take a look at. Picture used courtesy of Steve Arar
The ramp interval (0.29 seconds) is way bigger than the time between the samples, which could be described utilizing the next equation:
$$T~=~ frac{1}{f_{s}}~=~ frac{1}{40~textual content{kHz}}~=~ 25~mutext{s}$$
the place:
T is the time between samples in seconds
fs is the sampling frequency in Hz.
In different phrases, the ramp enter adjustments slowly with respect to the ADC sampling charge. This permits every ADC code to be “hit” a number of occasions.
If we accumulate 80,000 samples, we acquire the histogram proven in Determine 7.
Determine 7. Histogram of digital code occurrences for the instance ADC. Picture used courtesy of Steve Arar
Bin 5 has a zero depend, exhibiting that code 5 (101) is lacking. Inspecting the best ADC response (the purple curve in Determine 4) reveals that the width of a great step is the same as the voltage spacing between the primary and final transition factors divided by the variety of steps in between:
$$frac{6.5~LSB~ – ~0.5~LSB}{6}~=~1~LSB$$
Put in another way, the width of a great step is the same as the common width. The variety of occasions that codes possessing the best width (DNL = 0) happen is subsequently equal to the common code depend per bin. Excluding the primary and final bins, we are able to calculate the common variety of hits per bin as:
$$N_{Common} = frac{12500+15000+12500+7500+0+12500}{6}=10000$$
Dividing the bin heights by the common code depend offers us the normalized histogram in Determine 8.
Determine 8. Regular histogram distribution for instance ADC take a look at. Picture used courtesy of Steve Arar
The normalized histogram specifies the code width in least vital bits, and we decided beforehand that best steps have a top of 1 LSB. Realizing that, we are able to produce the DNL data (Determine 9) by subtracting 1 LSB from the normalized bin counts of Determine 8. Our outcomes listed here are in keeping with the DNL plot in Determine 5.
Determine 9. DNL for the instance ADC. Picture used courtesy of Steve Arar
With correct precautions, the linear ramp histogram methodology can be utilized to measure the differential nonlinearity of ADCs with 16 bit or increased decision. Precisely measuring integral nonlinearity (INL) is more difficult.
Utilizing a Linear Ramp Histogram Check to Measure INL
The INL specification describes the deviation of the particular switch perform’s transition factors from the best values. The INL is the cumulative impact of the DNL errors, so the INL of the m-th code could be discovered by making use of the next equation:
$$INL[m]=sum_{i=1}^{m-1}DNL[i]$$
In precept, the DNL data could be plugged into the above equation to find out the INL error. In apply, nevertheless, there are a number of error sources that forestall us from measuring INL precisely.
The variation of take a look at circuit parameters and ADC traits contribute to INL measurement errors. The take a look at circuit variations can come from the ability provide, the voltage reference, or the enter sign generator; changeable ADC traits embody the offset and achieve.
The summation within the equation above inherently accumulates all of those errors over the measurement time, probably resulting in faulty outcomes for linearities above 10 bits.
A gradual measurement system can exacerbate the drift problem—if it might probably’t sustain with the ADC’s excessive sampling charge, gathering the required variety of samples would require an extended measurement time. If the drift error is the limiting issue, we may use a quick Fourier rework (FFT) take a look at to measure the ADC harmonic distortion, which is the principal impact of INL. FFT exams require a a lot smaller variety of samples, making them much less delicate to float.
Moreover, a linear ramp histogram take a look at assumes that the enter ramp is completely linear. Any nonlinearity within the enter immediately interprets to an error in our INL measurements. This limits the usage of the ramp histogram-based INL measurement to ADCs of 12 bits or so. To get round this downside, we are able to use a sinusoidal enter for the histogram take a look at, since low-noise, pure sinusoidal inputs could be simply generated.
Up Subsequent
On this article, we targeted on the linear ramp histogram take a look at—each its usefulness and its limitations. Subsequent time we’ll focus on the sinusoidal histogram take a look at, which addresses a few of these limitations.
Featured picture used courtesy of Adobe Inventory